Patent attributes
A memory system includes a memory chip, a queue block and a memory controller. The queue block is configured to store a command to be transmitted to the memory chip. The queue block includes a first queue and a plurality of second queues each corresponding to a plane of the memory chip. The memory controller is configured to determine whether or not a first command enqueued in the first queue is a first read command. The first read command is a command for executing read operation in the planes asynchronously. When the first command is the first read command, the memory controller transfers the first command to one of the second queues corresponding to a plane in which the first command is to be executed. The memory controller selects the first queue or the second queues as a source of a command to be transferred to the memory chip.
