US Patent 10950610 Asymmetric gate cut isolation for SRAM

Methods of forming a gate cut isolation for an SRAM include forming a first and second active nanostructures adjacent to each other and separated by a space; forming a sacrificial liner over at least a side of the first active nanostructure facing the space, causing a first distance between a remaining portion of the space and the first active nanostructure to be greater than a second distance between the remaining portion of the space and the second active nanostructure. A gate cut isolation is formed in the remaining portion of the space such that it is closer to the second active nanostructure than the first active nanostructure. The sacrificial liner is removed, and gates formed over the active nanostructures with the gates separated from each other by the gate cut isolation. An SRAM including the gate cut isolation and an IC structure including the SRAM are also included.