A system comprises a first computer interface that includes a first plurality of single bit bus lines that communicate with a computer accessory; and a second computer interface that includes a second plurality of single bit bus lines that communicate with a vehicle computer. The second plurality of single bit bus lines are less than the first plurality of single bit bus lines for preventing bits of the data bits that are on a most significant bit (MSB) bus of the first plurality of single bit bus lines from communicating with a region of an address space in a memory of the on-board vehicle computer.