US Patent 10957376 Refresh testing circuit and method

A refresh testing circuit and method are provided. The refresh testing circuit includes an internal clock generator, a counter, and an address detection circuit. The internal clock generator transmits a control clock signal to a refresh controller to generate a bank selection signal and a row address signal for a refresh operation. The counter counts variations of the bank selection signal to generate a count value. The address detection circuit detects whether a value of the row address signal is sequentially increased during the refresh operations to generate a detection signal.