Patent attributes
A semiconductor structure includes a substrate and a channel stack disposed over a portion of a top surface of the substrate, the channel stack including two or more nanosheet channels, inner spacers disposed above and below outer edges of the two or more nanosheet channels, work function metal disposed between the inner spacers above and below each of the two or more nanosheet channels, and a dielectric layer disposed between the work function metal and the inner spacers and two or more nanosheet channels. The semiconductor structure further includes source/drain regions disposed over the top surface of the substrate surrounding the channel stack and a gate region disposed over a top surface of the channel stack, the gate region including the work function metal and a gate metal disposed over the work function metal. The semiconductor structure further includes a capping layer and contacts.
