US Patent 10964717 Methods and apparatus for three-dimensional NAND structure fabrication

Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. In some embodiments, the method, for example, includes forming, on a substrate, a stack of alternating layers including a first layer of material and a second layer of material different from the first layer of material; forming a memory hole in the stack of alternating layers of the first layer of material and the second layer of material; depositing a layer of blocking oxide on sides defining the memory hole; depositing a layer of silicon atop the layer of blocking oxide to form a silicon channel; deposit core oxide to fill the silicon channel; removing the first layer of material to form spaces between the alternating layers of the second material; and one of depositing a third layer of material to partially fill the spaces to leave air gaps therein or depositing a fourth layer of material to fill the spaces.