US Patent 10970455 Apportionment aware hierarchical timing optimization

Methods and apparatus for creating an improved VLSI design. In-context timing analysis of a nominal VLSI design is performed and at least one assigned apportionment adjustment is determined for a sub-block of the nominal VLSI design. One or more slack adjustments are derived for at least one port of the sub-block based on the at least one apportionment adjustment and the one or more slack adjustments are applied to the in-context timing analysis to simulate a post optimization version of the sub-block. The in-context timing analysis is repeated using the one or more applied slack adjustments to generate the improved VLSI design.