US Patent 10977338 Reduced-area circuit for dot product computation

Some embodiments provide a method for executing a portion of a node of a machine-trained network. The method receives (i) multiple input values computed by previous nodes of the machine-trained network and (ii) for each of the input values, a corresponding predefined weight value. Each of the weight values is zero, a positive value, or a negation of the positive value. To compute a dot product of the input values with the weight values, the method passes to an adder circuit the input value for each input value with a corresponding positive weight value, the value zero for each input value with a corresponding weight value of zero, and a binary inversion of the input value for each input value with a corresponding negative weight value. After the adder circuit adds the values passed to it, the method adds an additional value based on the number of negative weight values.