US Patent 10978118 DDR SDRAM signal calibration device and method

Disclosed is a DDR SDRAM signal calibration device capable to adapting to the variation of voltage and/or temperature. The device includes: an enablement signal setting circuit configured to generate data strobe (DQS) enablement setting; a signal pad configured to output a DQS signal; a signal gating circuit configured to generate a DQS enablement setting signal and a DQS enablement signal according to the DQS enablement setting and then output a gated DQS signal according to the DQS enablement signal and the DQS signal; and a calibration circuit configured to output a calibration signal according to the DQS enablement setting signal and at least one of the DQS enablement signal and the DQS signal so that the enablement signal setting circuit can maintain or adjust the DQS enablement setting according to the calibration signal.