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US Patent 10985764 Phase detector offset to resolve CDR false lock

Patent 10985764 was granted and assigned to Xilinx on April, 2021 by the United States Patent and Trademark Office.

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Is a
Patent
Patent

Patent attributes

Patent Applicant
Xilinx
Xilinx
Current Assignee
Xilinx
Xilinx
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
10985764
Date of Patent
April 20, 2021
Patent Application Number
16918854
Date Filed
July 1, 2020
Patent Citations
‌
US Patent 10224937 Clock and data recovery circuit having tunable fractional-N phase locked loop
‌
US Patent 10484167 Circuit for and method of receiving a signal in an integrated circuit device
‌
US Patent 10038545 Systems and methods for clock and data recovery
‌
US Patent 10256968 Systems and methods for clock and data recovery
Patent Citations Received
‌
US Patent 11552643 Semiconductor integrated circuit and receiver device
Patent Primary Examiner
‌
Kenneth B Wells
Patent abstract

An example method of clock and data recovery (CDR) includes adding a pre-defined offset to an output of a phase detector (PD) of a CDR circuit, and loading an accumulator of a frequency loop of the CDR circuit with a pre-defined load value. The method further includes detecting the phase of an incoming signal using a PD, and determining that the CDR has locked onto a real lock point. In some examples, the method further includes determining that the CDR has locked on a real lock point, and, in response to the determination, modifying the pre-defined offset to equal zero.

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