US Patent 10992516 Efficient self-checking redundancy comparison in a network

In an embodiment, a computing node includes a computing circuit, a comparing circuit, and an indicator circuit. The computing circuit is configured to generate a first redundant message that corresponds to, and that is independent of, a source message propagating over a network during at least one time period. The comparing circuit is configured to compare information content of one or more corresponding portions of the source message and the first redundant message during each of the at least one time period to generate a comparison result. And the indicator circuit is configured to indicate whether the source message is valid or invalid in response to the comparison result. For example, such computing node can determine the validity of a redundant result with reduced processing overhead, reduced message delay, and reduced message latency as compared to existing computer nodes.