Patent attributes
An integrated semiconductor device having a gate structure adjacent to a semiconductor body at a channel region, the channel region being positioned laterally between source/drain regions. Metal plugs are on the source/drain regions, and rectangular-shaped or trapezoidal-shaped plug caps are above and immediately adjacent to the metal plugs. A self-aligned metal filled contact (CA) is conductively coupled to one of the metal plugs on the source and drain regions, and a self-aligned metal filled contact (CBoA) is conductively coupled to the gate structure. The device further includes a low k dielectric layer that includes a continuous airgap having an inverted u-shape formed about the gate structure and breaks at about a portion of the gate structure including the self-aligned metal filled contact (CBoA). Also, methods for forming the device including the uniquely shaped continuous airgap are disclosed.
