US Patent 11011651 Tight pitch stack nanowire isolation

Embodiments of the present invention include a tight pitch stack nanowire semiconductor device. The semiconductor device includes an active region including a blanket dielectric nanosheet. Further included are at least one fin formed on the blanket dielectric nanosheet. There is at least one gate structure formed over the at least one fin in the active region such that the blanket dielectric nanosheet forms an insulating layer between each of the at least one fin and the at least one gate structure, and a substrate such that each of the at least one fin and each of the at least one dummy gate are electrically isolated.