US Patent 11018676 Coarse delay lock estimation for digital DLL circuits
Patent 11018676 was granted and assigned to Intel on May, 2021 by the United States Patent and Trademark Office.
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Patent abstract
Digital delay locked loop circuits, devices systems, and associated methods are provided and described. Such devices, systems, and methods utilize an open loop measurement for establishing a coarse delay lock.
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Patent Inventor Names
Dan Shi0
Fangxing Wei0
Khushal Chandan0
Michael Allen0
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Patent Jurisdiction
Patent Number
110186760
Date of Patent
May 25, 2021
0Patent Application Number
163921840
Date Filed
April 23, 2019
0Official Website
Patent Primary Examiner
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US Patent 11018676 Coarse delay lock estimation for digital DLL circuits
Infobox
Is a
Patent applicant
Current assignee
Patent jurisdiction
Patent number
11018676
Date of patent
May 25, 2021
Patent application number
16392184
Date Filed
April 23, 2019
Patent primary examiner
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