Patent attributes
A phase-locked loop circuit included in a computer system includes time-to-digital converter and digital-to-time converter circuits. During a mode to test the time-to-digital converter circuit, the digital-to-time converter circuit is coupled to the time-to-digital converter circuit in a loop-back fashion. A control circuit supplies stimulus codes to the digital-time-converter circuit, which generates multiple delayed versions of a reference clock signal using the stimulus codes. The time-to-digital converter circuit, in turn, generates capture codes based on the delay between the reference clock signal and the delayed versions of the reference clock signal. The control circuit compares the capture codes to the stimulus codes to determine a linearity of a response of the time-to-digital converter circuit.
