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US Patent 11037635 Power management for multi-plane read operations
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Patent
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Date Filed
February 6, 2020
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Date of Patent
June 15, 2021
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Patent Application Number
16784171
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Patent Citations
US Patent 10026486 First read countermeasures in memory
US Patent 10402314 Self-management memory system and operating method thereof
US Patent 10235294 Pre-read voltage pulse for first read error handling
US Patent 10043558 Independent multi-plane read and low latency hybrid read
Patent Citations Received
US Patent 11521688 Power reduction during open and erased block reads of memory based on the position of last written word line of a memory block
US Patent 11657883 Isolating problematic memory planes to avoid neighbor plan disturb
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Patent Inventor Names
Yu-Chung Lien
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Huai-Yuan Tseng
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Tomer Eliash
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11037635
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Patent Primary Examiner
Pho M Luu
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