US Patent 11048435 Memory controller and method of operating the same

Provided herein may be a memory controller and a method of operating the same. The memory controller may control a write operation of a memory device in response to a write command received from a host. The memory controller includes a host interface, a buffer, and a first processor. The host interface is configured to receive write data corresponding to the write command from the host. The buffer is configured to store the write data. The first processor is configured to control operations of the host interface and the buffer. The first processor is configured to, when the write command is received, set an operation mode based on an operating status of the memory controller.