US Patent 11049554 SRAM array

SRAM arrays are provided. In each SRAM cell arranged in a column of cell array, a pull-down transistor and a pass-gate transistor are formed in P-type well region. A pull-up transistor is formed in N-type well region. At least one well strap cell includes an N-well strap structure formed on the N-type well region and a P-well strap structure formed on the P-type well region. A first distance between the active region of the N-well strap structure and the P-type well region is greater than a second distance between an active region of the pull-up transistor and the P-type well region.