Patent attributes
A memory device having improved read reliability includes: first blocks coupled to a first global line group and second blocks coupled to a second global line group; a voltage generator configured to generate an operating voltage for an operation performed on the first blocks and the second blocks; a block decoder configured to generate a block select signal for selecting a memory block on which a main operation is to be performed from among the first blocks as a selected block; and a block voltage controller configured to control the block decoder and the voltage generator to: perform a channel initializing operation of discharging channel regions of the selected block and a shared block which is selected from among the second blocks according to the block select signal; and perform a word line floating operation on the selected block and the shared block after the channel initializing operation.
