Patent attributes
A semiconductor chip is provided. The semiconductor chip includes a memory cell and a logic cell disposed aside the memory cell, and includes signal and ground lines with the memory and logic cells located therebetween. The memory cell includes first and second active structures extending along a first direction, and includes a storage transmission gate line, first through third gate lines and a read transmission gate line extending along a second direction. The storage transmission gate line includes first and second line segments, which respectively extends across the active structures. The first through third gate lines continuously extend across the first and second active structures. The read transmission gate line includes third and fourth line segments, which respectively extend across the active structures. The first through third gate lines are located between the storage and read transmission gate lines.
