US Patent 11062765 Semiconductor integrated circuit device

In an SRAM cell using vertical nanowire (VNW) FETs, transistors (PD1, PD2) constituting a drive transistor are placed on both sides of a transistor (PU1) in an X direction, and transistors (PD3, PD4) constituting a drive transistor are placed on both sides of a transistor (PU2) in the X direction. An access transistor (PG1) is placed on one-hand side in the X direction of the transistor (PU1), and an access transistor (PG2) is placed on the other-hand side in the X direction of the transistor (PU1).