US Patent 11063053 Integrated circuit and static random access memory thereof

An SRAM structure comprises first and second semiconductor fins, and a gate structure. The first semiconductor fin is formed within a P-well region. The second semiconductor fin is formed within an N-well region abutting the P-well region. The gate structure extends across the first semiconductor fin and the second semiconductor fin, and forms a pull-down transistor with the first semiconductor fin and a pull-up transistor with the second semiconductor fin. The gate structure comprises a first work function metal layer extending within the P-well region and a second work function metal layer extending from the first work function metal layer to within the N-well region, and the second work function metal layer is thicker than the first work function metal layer.