Patent attributes
Devices and methods for a vertical field effect transistor (VTFET) semiconductor device include recessing a gate dielectric and a gate conductor of a vertical gate structure below a top of a vertical fin to form openings between the top of the vertical fin and an etch stop layer, the top of the vertical fin being opposite to a substrate at a bottom of the vertical fin. A spacer material is deposited in the openings to form a spacer corresponding to each of the openings. Each spacer is recessed below the top of the vertical fin. A top spacer is selectively deposited in each of the openings to line the etch stop layer and the spacer such that the top of the vertical fin is exposed above the top spacer and the spacer is covered by the top spacer. A source/drain region is formed on the top of the vertical fin.
