US Patent 11068408 Memory system and operating method thereof

A memory system includes a nonvolatile memory device, a buffer memory device storing logical-physical address mapping information, and a memory controller controlling operations of the nonvolatile and buffer memory devices. The memory controller comprises a cache memory, a host control circuit, a flash translation section, and a flash control circuit. The host control circuit receives a read command and a read logical address from a host, reads mapping information corresponding to the read logical address from the buffer memory device, and caches the mapping information in the cache memory, the mapping information corresponding to the logical-physical address mapping information stored in the buffer memory device. The flash translation section reads a read physical address mapped to the read logical address from the mapping information. The flash control circuit reads data corresponding to the read command from the nonvolatile memory device based on the read physical address.