US Patent 11069784 Semiconductor device and method of manufacture

FinFET devices with source/drain contacts with reduced resistance/capacitance power loss and with an enhanced processing window between the source/drain contacts and a gate via and methods of manufacture are described herein. A metal riser may be formed in a first recess of a source/drain contact of a first material. The metal riser and a contact via may be formed from a second material and the contact via may be formed over the metal riser to provide a hybrid source/drain contact of a finFET with a wide surface contact area at an interface between the source/drain contact and the metal riser. A dielectric fill material and/or a conformal contact etch stop layer may be used to form an isolation region in a second recess of the source/drain contact to extend a processing window disposed between the isolation region and a gate contact of the finFET.