Patent attributes
Described herein are IC devices that include semiconductor nanoribbons stacked over one another to realize high-density 3D SRAM. An example device includes an SRAM cell built based on a first nanoribbon, suitable for forming NMOS transistors, and a second nanoribbon, suitable for forming PMOS transistors. Both nanoribbons may extend substantially in the same plane above a support structure over which the memory device is provided. The SRAM cell includes transistors M1-M4, arranged to form two inverter structures. The first inverter structure includes transistor M1 in the first nanoribbon and transistor M2 in the second nanoribbon, while the second inverter structure includes transistor M3 in the first nanoribbon and transistor M4 in the second nanoribbon. The IC device may include multiple layers of nanoribbons, with one or more such SRAM cells in each layer, stacked upon one another above the support structure, thus realizing 3D SRAM.
