Patent attributes
A semiconductor memory device includes first and second planes of memory cells, and a control circuit configured to perform a write operation on the memory cells to store first and second bits per memory cell, and to perform a first read operation using a first read voltage to read the first bits and a second read operation using second and third read voltages to read the second bits. In response to a first instruction, the control circuit performs the first and second read operations to read the first bits from the first plane and the second bits from the second plane, respectively. In response to a second read instruction, the control circuit performs the second and first read operations to read the second bits from the first plane and the first bits from the second plane, respectively.
