US Patent 11139970 Efficient hardware architecture for highly secure isogeny-based cryptosystems

A computer processing hardware architecture system in a highly secure isogeny based cryptosystem that includes at least one computer processor operably configured to target accelerating operations involved in isogenies on elliptic curves and having a secret key register operably configured to register a secret key, a pseudo-random function, and a secret message buffer, each operably written to by a 2:4 demultiplexer circuit operably configured to receive outside data in regions therein and read by a 4:2 multiplexer circuit.