Patent attributes
The disclosure relates to a processor including an N-bit data bus configured to access a memory; a central processing unit CPU connected to the data bus; a coprocessor coupled to the CPU, including a register file with N-bit registers; an instruction processing unit in the CPU, configured to, in response to a load-scatter machine instruction received by the CPU, read accessing a memory address and delegating to the coprocessor the processing of the corresponding N-bit word presented on the data bus; and a register control unit in the coprocessor, configured by the CPU in response to the load-scatter instruction, to divide the word presented on the data bus into K segments and writing the K segments at the same position in K respective registers, the position and the registers being designated by the load-scatter instruction.
