Patent attributes
A semiconductor structure disposed on a substrate including a first metal layer disposed on the substrate, a gate insulating layer disposed on the substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopping pattern disposed on the oxide semiconductor layer, and a second metal layer disposed on the etch stopping layer. The first metal layer includes a gate line. The gate insulating layer covers the gate line. Patterning of the oxide semiconductor layer defines an oxide semiconductor pattern. The second metal layer includes a source electrode and a drain electrode electrically connected to the oxide semiconductor pattern. The etch stopping layer is located between the second metal layer and the oxide semiconductor layer. The second metal layer includes a signal line disposed on the etch stopping layer and is electrically connected to the oxide semiconductor pattern. A manufacturing method of the semiconductor structure is also provided.