Patent attributes
An apparatus includes a plurality of main word line circuits. Each main word line circuit drives a respective global word line to one of an active state value, an intermediate voltage state, or a pre-charge state. The intermediate voltage state voltage is below the active state voltage and above the pre-charge state voltage. The memory device also includes a plurality of sub-word line drivers. Each sub-word line driver is connected to a corresponding global word line and configured to drive a respective local word line between the corresponding global word line voltage and a low voltage value. The apparatus further includes a plurality of phase drivers. Each phase driver is connected to a predetermined number of sub-word line drivers, where each of the predetermined number of sub-word line drivers connects to a different global word line.
