US Patent 11177001 3D NAND flash and operation method thereof

A programming method of an increment step pulse program (ISPP) for a three-dimension (3D) NAND flash includes programming a select wordline of an unselect bit line of the 3D NAND flash; performing a first verification process with at least a verification voltage on the select wordline; determining whether a first verification voltage of the first verification process for the select wordline is higher than a default voltage or not; and removing a pre-pulse phase of the ISPP when the first verification voltage is higher than the default voltage; wherein the first verification voltage is a following verification voltage of the first verification process.