US Patent 11177229 IC chip layout for minimizing thermal expansion misalignment
Patent 11177229 was granted and assigned to Synaptics on November, 2021 by the United States Patent and Trademark Office.
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Patent abstract
An integrated circuit (IC) chip comprises a plurality of pads and a plurality of bumps. The plurality of pads includes a first pad. The plurality of bumps is disposed on the plurality of pads. The plurality of bumps includes a first bump disposed on the first pad. The first bump as a width that is different than an exposed with of the first pad. The center of the first bump is not aligned with a center of the first pad.
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Patent Inventor Names
Hiromasa Hiura0
Naoki Hasegawa0
Shinya Suzuki0
Yuichi Nakagomi0
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Official Website
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Patent Applicant
Current Assignee
Patent Jurisdiction
Patent Number
111772290
Date of Patent
November 16, 2021
0Patent Application Number
168380470
Date Filed
April 2, 2020
0Official Website
Patent Primary Examiner
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Edits on 19 Nov, 2021
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US Patent 11177229 IC chip layout for minimizing thermal expansion misalignment
Infobox
Is a
Patent applicant
Current assignee
Patent jurisdiction
Patent number
11177229
Date of patent
November 16, 2021
Patent application number
16838047
Date Filed
April 2, 2020
Patent primary examiner
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