Patent attributes
VTFET devices with bottom source and drain extensions are provided. In one aspect, a method of forming a VTFET device includes: patterning vertical fin channels in a substrate; forming sidewall spacers along the vertical fin channels having a liner and a spacer layer; forming recesses at a base of the vertical fin channels; indenting the liner; annealing the substrate under conditions sufficient to reshape the recesses; forming bottom source and drains in the recesses; forming bottom source and drain extensions in the substrate adjacent to the bottom source and drains; removing the sidewall spacers; forming bottom spacers on the bottom source and drains; forming gate stacks over the bottom spacers alongside the vertical fin channels; forming top spacers over the gate stacks; and forming top source and drains at tops of the vertical fin channels. A VTFET device by the method having bottom source and drain extensions is also provided.
