US Patent 11188465 Cache memory replacement policy

A cache memory is disclosed. The cache memory includes a plurality of ways, each way including an instruction memory portion, where the instruction memory portion includes a plurality of instruction memory locations configured to store instruction data encoding a plurality of CPU instructions. The cache memory also includes a controller configured to determine that each of a predetermined number of cache memory hit conditions have occurred, and a replacement policy circuit configured to identify one of the plurality of ways as having experienced a fewest quantity of hits of the predetermined number of cache memory hit conditions, where the controller is further configured to determine that a cache memory miss condition has occurred, and, in response to the miss condition, to cause instruction data retrieved from a RAM memory to be written to the instruction memory portion of the way identified by the replacement policy circuit.