US Patent 11189328 Semiconductor devices and semiconductor systems

A semiconductor device includes an input control circuit and an internal command generation circuit. The input control circuit is synchronized with a first pulse of an internal clock signal to generate an internal chip selection signal and a first internal command/address signal from a chip selection signal and a command/address signal. In addition, the input control circuit is synchronized with a second pulse of the internal clock signal to inhibit generation of the internal chip selection signal. The internal command generation circuit generates a first active command and a second active command which are sequentially enabled when the internal chip selection signal and the first internal command/address signal have a predetermined logic level combination.