US Patent 11189555 Chip packaging with multilayer conductive circuit

A semiconductor device includes a substrate and a chip. The substrate has a first conduction layer, a second conduction layer, and an isolation layer disposed between the first conduction layer and the second conduction layer. The first conductive layer has a first portion and a second portion spaced apart from the first portion, and each of the first portion and the second portion includes a main part and a plurality of extension parts extending from the main part. The chip is disposed on the extension parts of the first portion and the second portion of the first conductive layer.