Patent attributes
A memory structure and formation method are provided. The memory structure can comprise two second grooves along the row direction in each active area. The two second grooves divides each active area into a drain and two sources located on both sides of the drain. The surface of the insulating layer is lower than bottom surface of the second groove. A third groove is formed on the insulating layer between the first anti-etching dielectric layer and the second anti-etching dielectric layer to expose at least part of the surface of the sidewalls on both sides of the active area at the bottom of the second grooves and part of the surface of the sidewalls of the source and drain on both sides of the second grooves. The third groove is in connection with the second groove. A gate structure is formed in the second groove and the third groove.
