US Patent 11189791 Integrated circuit and fabrication method thereof

A method for fabricating an integrated circuit is provided. The method includes forming a memory cell over a substrate, wherein the memory cell comprising a top electrode, a bottom electrode, and a resistance switching element between the bottom electrode and the top electrode; forming a dielectric layer over the memory cell and the substrate; etching a via opening in the dielectric layer to expose the top electrode of the memory cell; forming a spacer in the via opening; performing a liner removal process to the dielectric layer after forming the spacer; and forming a conductive feature connected to the top electrode in the via opening.