US Patent 11195589 Memory cell arrangement and methods thereof

According to various aspects, a memory cell arrangement is provided, the memory cell arrangement including a control circuit configured to carry out a de-trapping writing scheme to write at least one memory cell of the memory cell arrangement into a memory state, the de-trapping writing scheme including providing one or more write voltage pulses and one or more de-trapping voltage pulses at the at least one memory cell, wherein the one or more de-trapping voltage pulses have opposite polarity with respect to the one or more write voltage pulses, and wherein one or more properties of the one or more write voltage pulses and of the one or more de-trapping voltage pulses are varied as long as the memory cell is not in the memory state.