US Patent 11200866 Low latency composer

In some aspects, the present disclosure provides a method for generating a frame. The method includes receiving a first fence indicating that a first frame stored in a display processor unit (DPU) buffer has been consumed by a hardware component. The method also includes in response to receiving the first fence, fetching a plurality of layers from an application buffer, the plurality of layers corresponding to a second frame. The method also includes determining to use both a DPU and a graphics processing unit (GPU) to process the plurality of layers for composition of the second frame. The method also includes fetching the first fence from the DPU buffer and generating a second fence.