US Patent 11200958 Memories for mitigating program disturb

Memories might include an array of memory cells comprising a plurality of strings of series-connected memory cells and a controller for access of the array of memory cells, wherein the controller is configured to perform a sense operation on a particular memory cell of a string of series-connected memory cells, discharge the access line for a second memory cell of the string of series-connected memory cells to a first voltage level and discharge the access line for the particular memory cell to a second voltage level higher than the first voltage level after completion of the sense operation, and discharge the access line for a third memory cell of the string of series-connected memory cells to a third voltage level lower than the second voltage level and higher than the first voltage level after initiating the discharge of the access line for the particular memory cell.