Patent attributes
Multiple ports of a network device are muxed together to form a single packed ingress interface into a buffer. A multiplexor alternates between the ports in alternating input clock cycles. Extra logic and wiring to provide a separate writer for each port is avoided, since the packed interface and buffer writers operate at higher speeds and/or have more bandwidth than the ports, and are thus able to handle incoming data for all of the ports coupled to the packed ingress interface. A packed ingress interface may also or instead support receiving data for multiple data units (e.g. multiple packets) from a single port in a single clock cycle, thereby reducing the potential to waste bandwidth at the end of data units. The interface may send the ending segments of the first data unit to the buffer. However, the interface may hold back the starting segments of the second data unit in a cache. In an embodiment, a gear shift merges the first part of each subsequent portion of the second data unit with the cached data to form a full-sized data unit portion to send downstream, while the second part of the portion replaces the cached data. When the end of the second data unit is detected, if any segments of the second data unit remain after the merger process, the remainder is sent downstream as a separate portion at the same time.
