US Patent 11216308 Communication architecture for exchanging data between processing units

A communication architecture, for exchanging data between processing units that are intended to operate in parallel comprises a communication system comprising a set of interfaces each intended to be linked to a processing unit, a set of sequencers that are able to define, for each processing unit, time intervals of access to a shared memory accessible by the processing units for writing and reading data, for the sequential arbitration of accesses to said memory, and a set of address managers able to allocate each processing unit ports for access to the shared memory.