Patent attributes
A system may include a persistent storage device, a low latency cache device, a volatile memory; and a processor. The processor is to store a data structure in the volatile memory that is usable to directly translate a block logical address for targeted data to a candidate physical location on the cache device, store a multilevel translation index in the volatile memory for translating the block logical address for the targeted data to an expected physical location of the targeted data on the cache device and attempt accessing the targeted data at the candidate physical location retrieved from the direct cache address translation data structure. In response to the targeted data not being at the candidate physical address, access the targeted data at the expected physical location retrieved from the multilevel translation index.
