US Patent 11233002 High density low power interconnect using 3D die stacking

An electronic circuit is implementing using a first logic die, a second logic die, and an interposer array connecting the first logic die to the second logic die. The first logic die includes an array of output contacts. The second logic die includes an array of input contacts. The interposer array includes a plurality of interposer dice. Each interposer die includes a plurality of input contacts and a plurality of output contacts. The array of output contacts of the first logic die is bonded to at least a subset of input contacts from the plurality of input contacts of an interposer die of the plurality of interposer dice. The array of input contacts of the second logic die is bonded to at least a subset of output contacts from the plurality of output contacts of the interposer die of the plurality of interposer dice.