US Patent 11244853 Fully aligned via interconnects with partially removed etch stop layer

A dual damascene interconnect structure with a fully aligned via integration scheme is formed with a partially removed etch stop layer. Portions of the etch stop layer are removed prior to dual damascene patterning of an interlevel dielectric layer formed above metal lines and after such patterning. Segments of the etch stop layer remain only around the vias, allowing the overall capacitance of the structure to be reduced.