US Patent 11244861 Method and structure for forming fully-aligned via

A method for manufacturing a semiconductor device includes forming a first dielectric layer, and forming a second dielectric layer stacked on the first dielectric layer. In the method, a plurality of conductive lines are formed in the first and second dielectric layers, and the plurality of conductive lines are recessed to form a plurality of openings in the second dielectric layer. The method also includes forming a plurality of dielectric fill layers on the plurality of conductive lines in the plurality of openings. At least one of the plurality of dielectric fill layers is selectively removed with respect to the second dielectric layer to expose a conductive line of the plurality of conductive lines, and a via is formed in place of the selectively removed dielectric fill layer.