Patent attributes
A semiconductor device including a lower structure, an upper pattern, a stacked structure, a separation structure passing through the stacked structure, a vertical structure comprising a channel layer, wherein the stacked structure comprises a plurality of interlayer insulating layers and a plurality of gate layers, the lower structure comprises a first lower pattern and a second lower pattern of a material different from a material of the first lower pattern, the first lower pattern comprises a first portion between the second lower pattern and the channel layer, a second portion extending from the first portion to a region between the second lower pattern and the upper pattern, and a third portion extending from the first portion to a region between the second lower pattern and the substrate structure, and the first lower pattern does not extend toward a side surface of the upper pattern.
