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Patent attributes
Patent Jurisdiction
Patent Number
Date of Patent
February 15, 2022
Patent Application Number
16961383
Date Filed
October 15, 2018
Patent Primary Examiner
Patent abstract
Power consumption of a time-to-digital converter (TDC) used in a phase locked loop (ADPLL) is suppressed. The time-to-digital converter includes an analog-to-digital converter and a current source circuit. The analog-to-digital converter includes a predetermined charge capacitor. The current source circuit supplies a charge current that charges the charge capacitor of the analog-to-digital converter with a charge. The charge current supplied by the current source circuit is supplied so that a charge voltage at the time of charging the charge capacitor of the analog-to-digital converter with the charge current has a constant gradient with respect to a charge time.
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